library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use work.FAW_TYPES.all;

entity RefSampledPointsSRController is
    Port ( 
			  clk_rspsrc : in  STD_LOGIC;
			  reset_rspsrc : in STD_LOGIC;
           i_rspsrc : in  COUNTER_ROWS;
           j_rspsrc : in  COUNTER_COLUMNS;
			  we_rspsrc : out SR_ENABLE_ROWS;
           sclear_rspsrc : out  STD_LOGIC
			  );
end RefSampledPointsSRController;

architecture Behavioral of RefSampledPointsSRController is

begin


	processo:process(clk_rspsrc,reset_rspsrc)
		variable WE_VAR : SR_ENABLE_ROWS;
		variable J_VAR:integer;
		begin
		
			if(reset_rspsrc'event and reset_rspsrc='1' and clk_rspsrc='1')then
				for i in 0 to RSPSRC_SR_REGISTERS-1 loop
					WE_VAR(i):='1';
				end loop;
				sclear_rspsrc<='1';
			end if;
			
--			if(reset_rspsrc'event and reset_rspsrc='0' and clk_rspsrc='1')then
--				for i in 0 to RSPSRC_SR_REGISTERS-1 loop
--					WE_VAR(i):='0';
--				end loop;
--				sclear_rspsrc<='0';
--			end if;
			
	
			if (clk_rspsrc'event and clk_rspsrc='1') then
				
--				if(i_rspsrc=0 and j_rspsrc=0)then
--					sclear_rspsrc<='1';
--				end if;
				
				if(i_rspsrc=0 and j_rspsrc=1)then
					for i in 0 to RSPSRC_SR_REGISTERS-1 loop
						WE_VAR(i):='0';
					end loop;
					sclear_rspsrc<='0';
				end if;
				
				J_VAR:=j_rspsrc+2;--aperture anticipate
				
				for i in 0 to RSPSRC_SR_REGISTERS-1 loop
						WE_VAR(i):='0';--azzeriamo tutti e dopo rialziamo solo i clock necessari (stalliamo)
				end loop;
				
				if((i_rspsrc mod P=0)and(J_VAR mod P=0)) then
					WE_VAR((i_rspsrc/p) mod RSPSRC_SR_REGISTERS) := '1';
				end if;
			
			end if;
			
			we_rspsrc<=WE_VAR;
			
		end process;

end Behavioral;

